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NX2116/2116A/2116B/2117/2117A
SYNCHRONOUS PWM CONTROLLER WITH CURRENT LIMIT, POWER GOOD & OVER VOLTAGE
PRELIMINARY DATA SHEET Pb Free Product The NX2116/2117 family of products are synchronous n Bus voltage operation from 2V to 25V Buck controller IC designed for step down DC to DC n Power Good indicator available in NX2116 converter applications. They are optimized to convert n Fixed 300kHz, 600kHz and 1MHz for NX2116 and 300kHz, 600kHz for NX2117 family. bus voltages from 2V to 25V to as low as 0.8V output n Internal Digital Soft Start Function voltage. The NX2116 and 2117 offer an Enable pin that can be used to program the converter's start up voltage n Less than 50 nS adaptive deadband using an external divider from bus voltage. These prod- n Enable pin to program BUS UVLO for NX2116/2117 ucts operate at fixed internal frequency of 300kHz, ex- n Programmable current limit triggers latch out by sensing Rdson of cept that NX2116A operates at 600kHz and 2116B at Synchronous MOSFET 1MHz frequency. These products employ loss-less curn No negative spike at Vout during startup and rent limiting protection by sensing the Rdson of synshutdown chronous MOSFET followed by latch out feature. Feedback under voltage triggers Hiccup. Other features are; 5V gate drive, Power good indica- n tor, Adaptive deadband control, Internal digital soft start; n Vcc undervoltage lock out and shutdown capability via n the enable pin or comp pin. n
Vin1 +12V Vin2 +5V
R5 68k C3 39uF R3 10 C4 1uF
6 4 1
DESCRIPTION
FEATURES
Graphic Card on board converters Memory Vddq Supply On board DC to DC such as 2V to 3.3V, 2.5V or 1.8V ADSL Modem
APPLICATIONS
L2 1uH
TYPICAL APPLICATION
C5 1uF Cin 270uF,18mohm
D1 MBR0530T1
Vcc
BST
C7 0.1uF
2
OFF ON
R8 10k 2N3904 R7 10k
R6 12.4k C1 33pF C2 1.5nF R4 17.4k
NX2116A
EN Comp Fb Gnd
Hdrv SW OCP Ldrv Pgood
M1 L1 1uH
8
10 9 3 5
7 11
R11 3.7k
M2
Co 2x (220uF,12mohm)
Vout +1.8V,9A
+5V R10 1k
R2 16k
R1 20k R9 2.61k C8 1nF
Figure 1 - Typical application of 2116 Device NX2116CMTR NX2116ACMTR NX2116BCMTR NX2117CUTR NX2117ACUTR
Rev. 3.0 03/14/06
ORDERING INFORMATION
Frequency 300kHz 600kHz 1MHz 300kHz 600kHz Pb-Free Yes Yes Yes Yes Yes 1
Temperature 0 to 70oC 0 to 70o C 0 to 70o C 0 to 70o C 0 to 70o C
Package MLPD-10L MLPD-10L MLPD-10L MSOP-10L MSOP-10L
NX2116/2116A/2116B/2117/2117A
ABSOLUTE MAXIMUM RATINGS
VCC to GND & BST to SW voltage .................... -0.3V to 6.5V BST to GND Voltage ........................................ -0.3V to 35V SW to GND ...................................................... -2V to 35V All other pins .................................................... -0.3V to VCC+0.3V or 6.5V Storage Temperature Range ............................... -65oC to 150oC Operating Junction Temperature Range ............... -40oC to 125oC ESD Susceptibility ........................................... 2kV CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
NX2116/2116A/2116B 10-LEAD PLASTIC MLPD
JA 52o C /W
BST 1 HDrv 2 LDrv 3 VCC 4 PGOOD 5 Gnd (PAD) 10 SW 9 OCP 8 COMP 7 FB 6 EN
BST 1 HDrv 2 GND 3 LDrv 4 VCC 5
NX2117/2117A 10-LEAD PLASTIC MSOP
JA 200o C/W
10 SW 9 OCP 8 COMP 7 FB 6 EN
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA= 0 to 70oC. Typical values refer to TA = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc) VCC Voltage Range VCC Supply Current (Static) VCC Supply Current (Dynamic) Supply Voltage(VBST) VBST Supply Current (Static) VBST Supply Current (Dynamic)
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SYM VREF
Test Condition
Min
TYP 0.8 0.2
MAX
Units V %
VCC ICC (Static) Outputs not switching CLOAD=3300pF ICC (Dynamic) FS=300kHz IBST (Static) Outputs not switching IBST CLOAD=3300pF (Dynamic) FS=300kHz
4.5
5 3 TBD
5.5
V mA mA
TBD TBD
mA mA
2
NX2116/2116A/2116B/2117/2117A
PARAMETER Under Voltage Lockout VCC-Threshold VCC-Hysteresis Oscillator Frequency SYM Test Condition Min 3.8 TYP 4 0.2 300 600 1000 1.5 95 0 2000 10 NX2116,NX2117 NX2116A, NX2117A NX2116B 6.8 MAX 4.2 Units V V kHz kHz kHz V % % umho nA mS VCC_UVLO VCC Rising VCC_Hyst VCC Falling FS 2116, 2117 2116A,2117A 2116B
Ramp-Amplitude Voltage Max Duty Cycle Min Duty Cycle Error Amplifiers Transconductance Input Bias Current EN & SS Soft Start time
VRAMP
Ib Tss
Enable HI Threshold Enable Hysterises High Side Driver (CL=3300pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time Low Side Driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Rise Time Fall Time Deadband Time OCP Adjust OCP current Power Good(Pgood) Threshold Voltage as % of Vref Hysteresis
Rev. 3.0 03/14/06
1.25 150
V mV
Rsource(Hdrv) Rsink(Hdrv)
I=200mA I=200mA
0.9 0.65 50 50 30
ohm ohm ns ns ns
THdrv(Rise) VBST-VSW=4.5V THdrv(Fall) VBST-VSW=4.5V Tdead(L to Ldrv going Low to Hdrv going High, 10%-10% H)
Rsource(Ldrv) Rsink(Ldrv)
I=200mA I=200mA
0.9 0.5 50 50 30
ohm ohm ns ns ns
TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10%
40 FB ramping up 90 5
uA % %
3
NX2116/2116A/2116B/2117/2117A
PIN DESCRIPTIONS
PIN SYMBOL VCC PIN DESCRIPTION Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. The maximum rating of this pin is 5V. This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capacitor is placed as close as possible to and connected to these pins and respected SW pins. Ground pin. This pin is the error amplifier inverting input. It is connected via resistor divider to the output of the switching regulator to set the output DC voltage. When FB pin voltage is lower than 0.6V, hiccup circuit starts to recycle the soft start circuit after 2048 switching cycles. This pin is connected to the drain of the external low side MOSFET via resistor and is the input of the over current protection(OCP) comparator. An internal current source 40uA is flown to the external resistor which sets the OCP voltage across the Rdson of the low side MOSFET. Current limit point is this voltage divided by the Rds-on. Once this threshold is reached the Hdrv and Ldrv pins are latched out. This pin is connected to source of high side FET and provides return path for the high side driver. It is also used to hold the low side driver low until this pin is brought low by the action of high side turning off. LDRV can only go high if SW is below 1V threshold . High side gate driver output. Low side gate driver output. An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc. When FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI state. A resistor divider is connected from the respective switcher BUS voltages to these pins that holds off the controller's soft start until this threshold is reached. An external low cost Transistor can be connected to this pin for external enable control. This pin is the output of error amplifier and is used to compensate the voltage control feedback loop. This pin can also be used to perform a shutdown if pulled lower than 0.3V.
BST GND
FB
OCP
SW
HDRV LDRV PGOOD
EN
COMP
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BLOCK DIAGRAM
VCC
FB 0.6V Bias Generator 1.25V 0.8V UVLO POR START Hiccup Logic
OC BST
EN 1.25/1.15
HDRV
SW OC START 0.8V OSC Digital start Up ramp S R FB 0.6V CLAMP START GND Q OC LDRV PWM Control Logic VCC
COMP
1.3V CLAMP Latch Out OCP comparator FB 0.9Vref /0.85Vref
40uA OCP
PGOOD
Figure 2 - Simplified block diagram of the NX2116
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APPLICATION INFORMATION
Symbol Used In Application Information:
VIN VOUT IOUT FS - Input voltage - Output voltage - Output current
IRIPPLE = =
VIN -VOUT VOUT 1 x x LOUT VIN FS
...(2) 12V-1.8V 1.8v 1 x x = 2.55A 1uH 12V 600kHz
DVRIPPLE - Output voltage ripple - Working frequency DIRIPPLE - Inductor current ripple
Output Capacitor Selection
Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load condition is determined by equation(3).
Design Example
The following is typical application for NX2116A, the schematic is figure 1. VIN = 12V VOUT=1.8V FS=600kHz IOUT=9A DVRIPPLE <=20mV DVDROOP<=100mV @ 9A step
VRIPPLE = ESR x IRIPPLE +
IRIPPLE 8 x FS x COUT ...(3)
Where ESR is the output capacitors' equivalent series resistance,COUT is the value of output capacitors. Typically when large value capacitors are selected such as Aluminum Electrolytic,POSCAP and OSCON types are used, the amount of the output voltage ripple is dominated by the first term in equation(3) and the second term can be neglected. For this example, POSCAP are chosen as output capacitors, the ESR and inductor current typically determines the output voltage ripple.
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency and efficiency. Larger inductor value normally means smaller ripple current. However if the inductance is chosen too large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
ESR desire =
VRIPPLE 20mV = = 7.8m IRIPPLE 2.55A
...(4)
If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 20mV output ripple, POSCAP ...(1) 2R5TPE220MC with 12m are chosen.
V -V V 1 L OUT = IN OUT x OUT x IRIPPLE VIN FS IRIPPLE =k x IOUTPUT
where k is between 0.2 to 0.4. Select k=0.3, then
12V-1.8V 1.8V 1 x x LOUT = 0.3 x 9A 12V 600kHz LOUT =0.94uH
N=
E S R E x IR I P P L E VR IPPLE
...(5)
Number of Capacitor is calculated as
N= 12mx 2.56A 20mV
Choose inductor from COILCRAFT DO3316P102HC with L=1uH is a good choice. Current Ripple is recalculated as
N =1.5 The number of capacitor has to be round up to a integer. Choose N =2. If ceramic capacitors are chosen as output ca
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pacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors . For example, one 100uF, X5R ceramic capacitor of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of ESR and capacitance is high and L L crit is true. In that case, the transient spec is dependent on the ESR of capacitor. In most cases, the output capacitors are multiple capacitors in parallel. The number of capacitors can be calculated by the following
N= ESR E x Istep Vtran + VOUT x 2 2 x L x C E x Vtran
with 2m ESR is used. The amount of output ripple is
VRIPPLE 2.56A = 2mx 2.55A + 8 x 600kHz x 100uF = 10.4mV
...(9)
where
Although this meets DC ripple spec, however it needs to be studied for transient requirement. Based On Transient Requirement Typically, the output voltage droop during transient is specified as: VDROOP 0 if L L crit = L x Istep - ESR E x CE V OUT
sient is 100mV for 9A load step.
if
L L crit
...(10)
For example, assume voltage droop during tranIf the POSCAP 2R5TPE220MC(220uF, 12m ) is used, the critical inductance is given as
Lcrit =
ESR E x C E x VOUT = Istep
12m x 220F x 1.8V = 0.56H 9A
The selected inductor is 1uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance. number of capacitors is
Vovershoot = ESR x Istep +
VOUT x 2 2 x L x COUT
...(6)
where is the a function of capacitor, etc.
= =
L x I step VOUT
- ESR E x C E
0 if L L crit = L x Istep - ESR x COUT V OUT
where
L crit =
if
L L crit
...(7)
1H x 9A - 12m x 220 F = 2.36us 1.8V
ESR E x Istep Vtran + VOUT x 2 2 x L x CE x Vtran
ESR x COUT x VOUT ESR E x C E x VOUT = Istep Istep
N=
...(8)
=
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected output inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the ESR
12m x 9A + 100mV 1.8V x (2.36us)2 2 x1H x 220F x100mV = 1.3
The number of capacitors has to satisfied both ripple and transient requirement. Overall, we can choose N=2.
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It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters.
FZ1 = FZ2 = FP1 = FP2 =
1 2 x x R 4 x C2 1 2 x x (R 2 + R3 ) x C3 1 2 x x R3 x C3 1 C x C2 2 x x R4 x 1 C1 + C2
...(11) ...(12) ...(13) ...(14)
where FZ1,FZ2,FP1 and FP2 are poles and zeros in the compensator. Their locations are shown in figure 4. The transfer function of type III compensator for transconductance amplifier is given by:
Ve 1 - gm x Z f = VOUT 1 + gm x Zin + Z in / R1
Compensator Design
Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response,compensator is employed to provide highest possible bandwidth and enough phase margin.Ideally,the Bode plot of the closed loop system has crossover frequency between1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with -20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen.
For the voltage amplifier, the transfer function of compensator is
Ve -Z f = VOUT Zin
To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R 4>>2/gm. And it would be desirable if R 1||R2||R3>>1/gm can be met at the same time.
Zin R3
Vout
Zf C1 C2 Fb gm Ve R4
A. Type III compensator design
For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III compensator by transconductance amplifier.
R2 C3 R1
Vref
Figure 3 - Type III compensator using transconductance amplifier
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NX2116/2116A/2116B/2117/2117A
Case 1: FLCGain(db)
power stage
FLC
40dB/decade
C3 = =
1 11 x( - ) 2 xx R2 Fz2 Fp1
loop gain
FESR
20dB/decade compensator
1 1 1 x( ) 2 x x 20k 7.6kHz 60.3kHz =916pF
R4 = =
VOSC 2 x x FO x L x x Cout Vin C3
1.5V 2 x x 50kHz x 1uH x x 440uF 12V 1nF =17.2k
Choose C3=1nF, R 4=17.4k. 5. Calculate C2 with zero Fz1 at 75% of the LC
FZ1 FZ2
FO FP1
FP2
double pole by equation (11).
C2 =
Figure 4 - Bode plot of Type III compensator Design example for type III compensator are in order. The crossover frequency has to be selected as FLC1 2 x x FZ1 x R 4
=
1 2 x x 0.75 x 7.6kHz x 17.4k = 1.6nF
Choose C2=1.5nF. 6. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency.
FLC = =
1 2 x x L OUT x C OUT 1
C1 = =
1 2 x x R 4 x FP2
2 x x 1uH x 440uF = 7.6kHz
1 2 x x 17.4k x 300kHz = 30pF
Choose C1=33pF
FESR =
1 2 x x ESR x C OUT
7. Calculate R 3 by equation (13).
1 = 2 x x 6m x 440uF = 60.3kHz
2. Set R2 equal to 20k.
R3 = =
1 2 x x FP1 x C3
1 2 x x 60.3kHz x 1nF = 2.64k
Choose R3=2.61k.
R1=
R 2 x VREF 20k x 0.8V = = 16k VOUT -VREF 1.8V-0.8V
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NX2116/2116A/2116B/2117/2117A
Case 2: FLCR1 =
R 2 x VREF 10k x 0.8V = = 8k VOUT -VREF 1.8V-0.8V
Gain(db)
power stage
Choose R1=8k. 3. Set zero FZ2 = FLC and Fp1 =FESR . 4. Calculate C3 .
FLC
40dB/decade
FESR
loop gain
C3 = =
1 11 ) x( 2 x x R2 Fz2 Fp1
1 1 1 ) x( 2 x x 10k 2.9kHz 8.2kHz =3.5nF
20dB/decade compensator
Choose C3=3.3nF. 5. Calculate R3 .
R3 = =
1 2 x x FP1 x C3
FZ1 FZ2 FP1 FO
FP2
1 2 x x 8.2kHz x 3.3nF = 5.9k
Choose R3 =5.9k. 6. Calculate R4 with FO=60kHz.
Figure 5 - Bode plot of Type III compensator (FLCR4 = =
VOSC 2 x x FO x L R2 x R3 x x Vin ESR R 2 + R3
1.5V 2 x x 60kHz x 1uH 10k x 5.9k x x 12V 6.5m 10k + 5.9k =26.9k Choose R4=26.7k. 5. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11).
C2 = =
1 2 x x FZ1 x R 4
FLC = =
1 2 x x L OUT x C OUT 1
1 2 x x 0.75 x 2.9kHz x 26.7k = 2nF
2 x x 1uH x 3000uF = 2.9kHz
Choose C2=2.2nF. 6. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency.
C1 =
FESR = = 1 2 x x ESR x COUT
1 2 x x R 4 x FP2
1 2 x x 6.5m x 3000uF = 8.2kHz
Rev. 3.0 03/14/06
1 2 x x 26.7k x 300kHz = 20pF =
Choose C1=22pF. 10
NX2116/2116A/2116B/2117/2117A
B. Type II compensator design
If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensator can be used to compensate the system. Type II compensator can be realized by simple RC circuit without feedback as shown in figure 7. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero location and constant gain.
Vout R2 Fb gm R1 Vref Ve R3 C2 C1
Gain=gm x
R1 x R3 R1+R2
... (15)
Figure 7 - Type II compensator with
1 Fz = 2 x x R3 x C1 Fp 1 2 x x R3 x C2
... (16) ... (17)
transconductance amplifier For this type of compensator, FO has to satisfy FLCpower stage Gain(db) 40dB/decade loop gain 20dB/decade
with 13m electrolytic capacitors. 1.Calculate the location of LC double pole F LC and ESR zero FESR.
FLC = =
1 2 x x L OUT x C OUT 1
2 x x 1uH x 3000uF = 2.9kHz
compensator Gain
FESR = =
1 2 x x ESR x C OUT
FZ FLC FESR
FO FP
R1 =
1 2 x x 6.5m x 3000uF = 8.2kHz
2.Set R2 equal to 1k.
Figure 6 - Bode plot of Type II compensator
R 2 x VREF 1k x 0.8V = = 800 VOUT -VREF 1.8V-0.8V
Choose R1=806. 3. Set crossover frequency at 1/10~ 1/5 of the swithing frequency, here FO=60kHz. 4.Calculate R3 value by the following equation.
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NX2116/2116A/2116B/2117/2117A
Vout
4.Calculate R3 value by the following equation.
R2
V 2 x x FO x L 1 VOUT R 3 = OSC x x x Vin RESR gm VREF 1.5V 2 x x 60kHz x 1uH 1 x x 12V 6.5m 2.0mA/V 1.8V x 0.8V =8.15k =
Choose R3 =8.2k. 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole. 1 C1 = 2 x x R 3 x Fz
1 = 2 x x 8.2k x 0.75 x 2.9kHz =8.9nF
Fb R1 Vref Voltage divider
Figure 8 - Voltage divider
Input Capacitor Selection
Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated as:
Choose C1=8.2nF. 6. Calculate C 2 by setting compensator pole Fp at half the swithing frequency.
1 C2= x R 3 x Fs = 1 x 8 .2k x 3 0 0 k H z =129pF
IRMS = IOUT x D x 1- D D= VOUT VIN
...(19)
VIN = 12V, VOUT=1.8V, IOUT=9A, using equation (19), the result of input RMS current is 3.2A. For higher efficiency, low ESR capacitors are recommended. One Sanyo OS-CON 16SP180M 16V 180uF 20m with 3.4A RMS rating is chosen as input bulk capacitors.
Choose C1=120pF.
Output Voltage Calculation
Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at 0.8V. The divider consists of two ratioed resistors so that the output voltage applied at the Fb pin is 0.8V when the output voltage is at the desired value. The following equation and picture show the relationship between
Power MOSFETs Selection
The power stage requires two N-Channel power MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter efficiency. In this design example, two IRFR3709Z are used. They have the following parameters: VDS=30V,RDSON =6.5m,QGATE =17nC. There are two factors causing the MOSFET power loss:conduction loss, switching loss. Conduction loss is simply defined as:
VOUT , VREF and voltage divider. .
R 1= R 2 x VR E F V O U T -V R E F
...(18)
where R2 is part of the compensator, and the value of R1 value can be set by voltage divider. See compensator design for R1 and R2 selection.
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PHCON =IOUT 2 x D x RDS(ON) x K PLCON =IOUT 2 x (1 - D) x RDS(ON) x K PTOTAL =PHCON + PLCON
...(20) sired voltage decided by the feedback resistor divider.
Vbus
+
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency. As a result, RDS(ON) should be selected for the worst case, in which K approximately equals to 1.4 at 125oC according to IRFR3709Z datasheet. Conduction loss should not exceed package rating or overall system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated.
OFF ON R2 10k R1 EN 1.25V/ 1.15V
POR Digital start up
Figure 9 - Enable and Shut down the NX2116 with Enable pin. The start up of NX2116 can be programmed through resistor divider at Enable pin. For example, if the input bus voltage is12V and we want NX2116 starts when Vbus is above 9V. We can select using the following equation.
1 PSW = x VIN x IOUT x TSW x FS ...(21) 2 where IOUT is output current, TSW is the sum of TR and TF which can be found in mosfet datasheet, and FS is switching frequency. Switching loss PSW is frequency dependent. Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET. MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.It is proportional to frequency and is defined as:
Pgate = (QHGATE x VHGS + QLGATE x VLGS ) x FS
R1 =
(9V - 1.25V) x R2 1.25V
The NX2116 can be turned off by pulling down the Enable pin by extra signal MOSFET as shown in the above Figure. When Enable pin is below 1.25V, the digital soft start is reset to zero. In addition, all the high side and low side driver is off and no negative spike will be generated during the turn off.
...(22)
where QHGATE is the high side MOSFETs gate charge,QLGATE is the low side MOSFETs gate charge,VHGS is the high side gate source voltage, and VLGS is the low side gate source voltage. This power dissipation should not exceed maximum power dissipation of the driver device.
Over Current Protection
Over current protection is achieved by sensing current through the low side MOSFET. An internal current source of 40uA flows through an external resistor connected from OCP pin to SW node sets the over current protection threshold. When synchronous FET is on, the voltage at node SW is given as
Soft Start and Enable
NX2116 has digital soft start for switching controller and has one enable pin for this start up. When the Power Ready (POR) signal is high and the voltage at enable pin is above 1.25V the internal digital counter starts to operate and the voltage at positive input of Error amplifier starts to increase, the feedback network will force the output voltage follows the reference and starts the output slowly. After 2048 cycles, the soft start is complete and the output voltage is regulated to the deRev. 3.0 03/14/06
VSW =-IL x RDSON
The voltage at pin OCP is given as
IOCP x ROCP +VSW
When the voltage is below zero, the over current occurss as shown in figure 10.
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NX2116/2116A/2116B/2117/2117A
vbus I OCP 40uA OCP R OCP OCP comparator SW
Figure 10 - Over current protection
The over current limit can be set by the following equation
ISET =
IOCP x ROCP K x RDSON
If MOSFET RDSON=6.5m, the worst case thermal consideration K=1.5 and the current limit is set at 15A, then
ROCP = ISET x K x RDSON 15A x 1.5 x 6.5m = = 3.656k IOCP 40uA
Choose ROCP=3.7k
Layout Considerations
The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to reduce the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point.
Rev. 3.0 03/14/06
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